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DATASHEET
Low Skew Dual Bank DDR I/II Fan-out Buffer
Description
Dual DDR I/II fanout buffer for VIA Chipset
AVDD2.5
ICS9P936
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND VDDQ2.5/1.8 AVDD2.5 AGND DDRT5 DDRC5 GND VDDQ2.5/1.8 DDRT4 DDRC4 DDRT3 DDRC3 SDATA SCLK
Output Features
* * * * * * * * * Low skew, fanout buffer SMBus for functional and output control Single bank 1-6 differential clock distribution 1 pair of differential feedback pins for input to output synchronization Supports up to 2 DDR DIMMs 266MHz (DDRI 533) output frequency support 400MHz (DDRII 800) output frequency support Programmable skew through SMBus Individual output control programmable through SMBus
AGND BUF_INT BUF_INC DDRT0 DDRC0 DDRT1 DDRC1 GND VDDQ2.5/1.8 FB_OUTT FB_OUTC DDRT2 DDRC2
Key Specifications
* * * * * OUTPUT - OUTPUT skew: <100ps Output Rise and Fall Time for DDR outputs: 650ps - 950ps DUTY CYCLE: 47% - 53% 28-pin SSOP/TSSOP package RoHS compliant packaging
28-SSOP & TSSOP
Funtional Block Diagram
BUF_INC BUF_INT
SCLK SDATA
Control Logic
ICS9P936
FB_OUTC FB_OUTT
DDRC (5:0) DDRT (5:0)
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME AVDD2.5 AGND BUF_INT BUF_INC DDRT0 DDRC0 DDRT1 DDRC1 GND VDDQ2.5/1.8 FB_OUTT FB_OUTC DDRT2 DDRC2 SCLK SDATA DDRC3 DDRT3 DDRC4 DDRT4 VDDQ2.5/1.8 GND DDRC5 DDRT5 AGND AVDD2.5 VDDQ2.5/1.8 GND PIN TYPE PWR PWR IN IN OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT IN I/O OUT OUT OUT OUT PWR PWR OUT OUT PWR PWR PWR PWR DESCRIPTION 2.5V Analog Power pin for Core PLL Analog Ground pin for Core PLL True Buffer In signal for memory outputs. Complementary Buffer In signal for memory outputs. -40 "Complementary" Clock of differential pair output. "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Ground pin. Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively True single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs. Complementary single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs. "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. "Complementary" Clock of differential pair output. "True" Clock of differential pair output. "Complementary" Clock of differential pair output. "True" Clock of differential pair output. Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively Ground pin. "Complementary" Clock of differential pair output. "True" Clock of differential pair output. Analog Ground pin for Core PLL 2.5V Analog Power pin for Core PLL Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively Ground pin.
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
Absolute Max
Supply Voltage Logic Inputs Ambient Operating Temperature Case Temperature Storage Temperature -0.5V to 3.6V GND -0.5 V to VDD +0.5 V or 3.6V, whichever is less 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters (VDDQ2.5/1.8 = 1.8V +/- 0.1V)
TA = 0 - 70C; Supply Voltage AVDD = 2.5V +/- 0.2V(unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Input Clamp Voltage High-level output voltage Low-level output voltage Input Capacitance Output Capacitance Input clock slew rate SYMBOL I IH I IL I DDAVDD2.5 CONDITIONS VI = VDDQ or GND VI = VDDQ or GND RL = 120, CL = 12pf @ 266MHz RL = 120, CL = 12pf @ 266MHz I OH = -9 mA I OL=9 mA VI = GND or VDDQ VOUT = GND or VDDQ Input clock 2 2 1 3 3 2.5 MIN -40 SPEC TYP MAX 10 26 180 -1.2 UNITS A A mA mA V V 0.6 4 4 4 V pF pF V/ns
23 164
I DDVDDQ2.5/1.8 VDDQ = 1.8V Iin = -18mA VIK VOH VOL CIN COUT t sl(i)
1.1
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
Recommended Operating Condition (VDDQ2.5/1.8 = 1.8V +/- 0.1V) (see note1)
TA = 0 - 70C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated) PARAMETER Low level input voltage High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) SYMBOL VIL VIH VIN DC - BUF_INT, BUF_INC VID AC - BUF_INT, BUF_INC V OX 0.6 V DDQ/2 - 0.1 VDDQ + 0.4 VDDQ/2 + 0.1 V V CONDITIONS BUF_INT, BUF_INC BUF_INT, BUF_INC 0.65 x V DDQ -0.3 0.3 VDDQ + 0.3 VDDQ + 0.4 MIN SPECIFICATION TYP MAX 0.35 x V DDQ UNITS V V V V
VIX
V DDQ/2 - 0.15
VDDQ/2
VDDQ/2 + 0.15
V
1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allow able DC excursion of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for sw itching, w here VTR is the true input level and VCP is the complimentary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at w hich the differential signal must be changed.
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
Timing Requirements VDDQ2.5/1.8 = 1.8 V +/- 0.1V
TA = 0 - 70C Supply Voltage AVDD2.5 = 2.5V+/-0.2V (unless otherwise stated) SPECIFICATION PARAMETER SYMBOL UNITS CONDITIONS -40 MAX Max clock frequency freqop 125 400 MHz Application Frequency Range Input clock duty cycle CLK stabilization freqApp dtin TSTAB 160 40 400 60 15 MHz % s
Switching Characteristics (VDDQ2.5/1.8 = 1.8V +/- 0.1V) (see note 1)
TA = 0 - 70C; Supply Voltage AVDD = 2.5V+/-0.2V, VDDQ2.5/1.8 = 1.8 V +/- 0.1V (unless otherwise stated) SPECIFICATION PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Period jitter -40 40 ps Period jitter Tjit (per) Half-period jitter T(jit_hper) Half period jitter -60 60 ps Cycle to Cycle Tcyc -Tcyc Cycle to Cycle jitter -40 40 ps Dynamic Phase Offset T(DPO) -50 50 ps -50 0 50 ps Static Phase Offset T(SPO) Output to Output Skew tskew DDR(0:5) 40 ps Output Duty Cycle tduty 47 53 ps Measured from 20% to 80% of Output clock slew rate tsl(i) 1.5 3 V/ns VDDQ 1. Switching characteristics guaranteed for operating frequency range
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
Electrical Characteristics - Input/Supply/Common Output Parameters (VDDQ2.5/1.8 = 2.5V +/- 0.2V)
TA = 0 - 70C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Input Clamp Voltage High-level output voltage Low-level output voltage Input Capacitance Output Capacitance Input clock slew rate SYMBOL I IH I IL CONDITIONS VI = VDD or GND VI = VDD or GND RL = 120, CL = 12pf @ 200MHz RL = 120, CL = 12pf @ 200MHz IOH = -12 mA IOL = 12 mA VI = GND or VDDQ VOUT = GND or VDDQ Input clock 2 2 1 3 3 2.5 1.7 0.6 4 4 4 MIN -10 SPEC TYP MAX 10 20 220 23 250 -1 UNITS A A mA mA V V V pF pF V/ns
IDDAVDD2.5 I DDVDDQ2.5/1.8 VIK VDDQ = 2.5V, Iin = -18mA VOH VOL CIN COUT tsl(i)
Recommended Operating Condition (VDDQ2.5/1.8 = 2.5V +/- 0.2V) (see note1)
TA = 0 - 70C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated) PARAMETER Low level input voltage High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) SYMBOL CONDITIONS VIL BUF_INT, BUF_INC BUF_INT, BUF_INC VIH VIN DC - BUF_INT, BUF_INC VID AC - BUF_INT, BUF_INC V OX VIX 0.7 V DDQ/2 - 0.15 V DDQ/2 - 0.2 VDDQ/2 VDDQ + 0.6 VDDQ/2 + 0.15 VDDQ/2 + 0.2 V V V SPECIFICATION TYP MAX UNITS V DDQ/2 - 0.18 V VDDQ/2 + 0.18 V MIN -0.3 0.36 VDDQ + 0.3 VDDQ + 0.6 V V
1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allow able DC excursion of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for sw itching, w here VTR is the true input level and VCP is the complimentary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at w hich the differential signal must be changed.
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
Timing Requirements VDDQ2.5/1.8 = 2.5V +/- 0.2V
TA = 0 - 70C Supply Voltage AVDD2.5 = 2.5V+/-0.2V (unless otherwise stated) SPECIFICATION PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 45 500 MHz Max clock frequency freqop Application Frequency Range freqApp 95 233 MHz Input clock duty cycle dtin 40 60 % CLK stabilization TSTAB 15 s
Switching Characteristics (VDDQ2.5/1.8 = 2.5V +/- 0.2V ) (see note 1)
TA = 0 - 70C; Supply Voltage AVDD = 2.5V+/-0.2V, VDDQ2.5/1.8 = 2.5 V +/- 0.2V (unless otherwise stated) SPECIFICATION PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Period jitter -60 60 ps Period jitter Tjit (per) Half-period jitter T(jit_hper) Half period jitter -75 75 ps Cycle to Cycle Jitter Tcyc -Tcyc Cycle to Cycle jitter -60 60 ps Static Phase Offset T(SPO) -50 0 50 ps Output to Output Skew Tskew DDR(0:5) 40 ps Output Duty Cycle tduty 47 53 ps Measured from 20% to 80% of 1.5 4 V/ns Output clock slew rate t sl(o) VDDQ 1. Switching characteristics guaranteed for operating frequency range
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4(H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D4(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
* * * * * * Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 * Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
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IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
I C Table: Output Control Register Byte 7 Pin # Name
Bit 7 Bit Bit Bit Bit Bit Bit Bit
2
2
Control Function
Frequency Detect FB_OUT Control Output Control Output Control Output Control Output Control Output Control Output Control
Type
RW RW RW RW RW RW RW RW
0
OFF Disable Disable Disable Disable Disable Disable Disable
1
ON Enable Enable Enable Enable Enable Enable Enable
Default
1 1 1 1 1 1 1 1
-
BUFF_IN_T/C FB_OUT_T/C DDR_T5/C5 DDR_T4/C4 DDR_T3/C3 DDR_T2/C2 DDR_T1/C1 DDR_T0/C0
6 5 4 3 2 1 0
I C Table: Byte Count Register Byte 8 Pin # Name
Bit Bit Bit Bit Bit Bit Bit Bit
2
Control Function
Type
RW RW RW RW RW RW RW RW
0
1
Default
0 0 0 0 1 1 1 1
7 6 5 4 3 2 1 0
-
BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Byte Count Programming b(7:0)
Writing to this register will configure how many bytes will be read back, default is 0h = 15 bytes
I C Table: Group Skew Control Register Pin # Name Byte 19
Bit 7 Bit Bit Bit Bit Bit Bit Bit
2
Control Function
DDR_C Skew Control (also see table1) Reserved Reserved FB_OUT Skew Control (also see table 2)
Type
RW RW RW RW RW RW RW RW
0
0000 = 0 0100 = 150 1000 = 300 1100 = 450 Reserved Reserved 00 = 0 01 = 250
1
1101 = 600 1110 = 750 1111 = 900 N/A Reserved Reserved 10 = 500 11 = 750
Default
0 0 0 0 0 0 0 0
-
6 5 4 3 2 1 0
DDR_CSkw3 DDR_CSkw2 DDR_CSkw1 DDR_CSkw0 Reserved Reserved FBOUTSkw1 FBOUTSkw0
I C Table: Group Skew Control Register Pin # Name Byte 20
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 DDR_TSkw3 DDR_TSkw2 DDR_TSkw1 DDR_TSkw0 Reserved Reserved Reserved Reserved
Control Function
DDR_T Skew Control (also see table1) Reserved Reserved Reserved Reserved
Type
RW RW RW RW RW RW RW RW
0
0000 = 0 0100 = 150 1000 = 300 1100 = 450 Reserved Reserved Reserved Reserved
1
1101 = 600 1110 = 750 1111 = 900 N/A Reserved Reserved Reserved Reserved
Default
0 0 0 0 0 0 0 0
Note: Bytes not shown are reserved and should not be altered.
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
28-pin SSOP Package Drawing and Dimensions
N
c
L
INDEX AREA
E1
E
12 D
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -2.00 -.079 A1 0.05 -.002 -A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 D SEE VARIATIONS SEE VARIATIONS E 7.40 8.20 .291 .323 E1 5.00 5.60 .197 .220 e 0.65 BASIC 0.0256 BASIC L 0.55 0.95 .022 .037 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 VARIATIONS N 28
10-0033
-Ce
b SEATING PLANE .10 (.004) C
D mm. MIN 9.90 MAX 10.50 MIN .390
D (inch) MAX .413
Reference Doc.: JEDEC Publication 95, MO-150
209 mil SSOP
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
28-pin TSSOP Package Drawing and Dimensions
4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) SYMBOL A A1 A2 b c D E E1 e L N aaa VARIATIONS N 28 D mm. MIN 9.60 MAX 9.80 MIN .378 D (inch) MAX .386 (25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
Part / Order Number 9P936AFLF 9P936AFLFT 9P936AGLF 9P936AGLFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP Temperature 0 to +70C 0 to +70C 0 to +70C 0 to +70C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. "A" denotes the revision designator (will not correlate to datasheet revision).
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
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ICS9P936 Low Skew Dual Bank DDR I/II Fan-out Buffer
Revision History
Rev. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 A B Description Updated Electrical Characteristics Updated Skew programming bytes and I2c programming address Updated LF Ordering Information Added TSSOP Ordering Information. Updated I2C. Updated Switching Characteristics. Updated Max Clock Frequency. Released to final. 1. Updated all electrical tables to specify VDDQ = 1.8V and 2.5V. 11/12/2009 2. Updated ordering information table 3. Updated pinout and pin descriptions 1.Corrected Byte 19/20 default to 00 hex. 12/2/2009 2.Corrected typos in electrical tables, made formatting improvements for readability. Issue Date 3/23/2005 4/1/2005 9/12/2005 9/14/2005 11/13/2006 4/5/2007 6/26/2007 4/8/2009 Page # 5-9 3, 10 11 12 3 6 1, 7, 10
Various
C
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TM
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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